Nishanth.Krishnappa@asu.edu

www.linkedin.com/pub/nishanth-krishnappa/43/649/690/

NISHANTH KRISHNAPPA

1010 E Orange Street, Apt #2, Tempe, AZ-85281

+1 203-873-7708

SUMMARY:

Computer Engineering graduate student with professional experience in an enterprise environment and specialization in the fields of

embedded systems and RTL design, actively looking for full time opportunities.

EDUCATION:

  · Master of Science: Computer Engineering, Arizona State University, Tempe, Arizona.

Expected graduation: Dec 14

PROJECTS:

Design of Linux based I2C Driver to access the on board EEPROM, Microchip 24FC256 EEPROM Oct 13

  · Modified and Developed an i2c client driver, such that the user program can read and write pages from the EEPROM

memory chip using the I2C driver architecture interface.

  · Asynchronous processing of EEPROM was achieved by revising the driver to handle non-blocking system calls and

implementing work queues.

Development of Resource Reservation Manager to handle virtual network set-up requests

  · Implemented a simplified model for resource reservation in physical network in C using pThreads library. The RR manager

accepts requests to set up a virtual network and for every request it spawns a thread to reserve the resources necessary for the

virtual network. It also provides a trace of the virtual network set-up request.

Design of Linux based Device Driver for HRT and Shared queues

Nov 13

Nov 13

  · Designed a device driver for high resolution timer , running on the system clock that offers a user specific functionality to

open, start, load, stop and read the counter value for the ARM architecture based DM3730 BeagleBoard XM.

  · Designed a device driver for a shared queue which performs basic enqueue and dequeue operations.

  · Developed a user application to initiate multiple threads using pThread library, accessing the shared queue and recording

their timestamps using HRT.

Parallel Programming using OpenMP and performance analysis

  · Analyzed the performance of the parallel C code on the ASU’s cluster Saguaro.

Development of a Parametric Cache Simulator

Oct 13

  · Implemented a C code for Monte Carlo min-cut algorithm for a graph, parallelized the serial code using OpenMP directives

and Intel Parallel Studio.

Mar 13

  · Implemented a parametric cache simulator in C and used it to design data caches suited to solve systems of linear equations.

  · The simulator modeled a memory hierarchy with data and victim cache. The eviction policy assumed was pseudo-least

recently used. The simulator provided cache statistics such as L1 reads/misses, Victim reads/misses, miss rate and total

memory traffic to/from main memory.

TECHNICAL SKILLS:

  · Languages: C, C++, Device Drivers, OpenMp, pThreads, Python, UML, Bash scripting, Assembly Language (MIPS),

VHDL, Verilog, System Verilog, VMM.

  · Internals and Packages: ARM-BeagleBoard-xm, GNU toolchain for ARM, Renesas RX63N board, Virtualization and

Hypervisors, Linux Real-Time PREEMPT Patch, gdb Debugger, Git, Cadence tools, hSpice, ModelSim, Aldec HDL,

Matlab, Intel Parallel Studio.

PROFESSIONAL EXPERIENCE:

Programmer Analyst, Cognizant Technology Solutions, Bangalore, India

  · Trained in Core Java, JavaScript, Oracle Database, certified IBM BPM developer with certification- IBM Certified Associate

BPM Developer - BPM Blueprint; Web Sphere Lombardi Edition V7.1.

Aug 11 to Dec 12

  · Development and QA testing of BPM software applications for clients such as Walgreens and Walmart using the modeling

tool, Teamworks 7.5.1., with a team of 8 members.

RELEVANT COURSE WORK:

Embedded Systems, Computer Architecture, Introduction to VHDL, Embedded Systems Programming, Operating Systems, Digital

Circuits and High Level Synthesis, Advanced Hardware System Design, Distributed Multiprocessor Operating Systems

  · Bachelor of Engineering: Electronics & Communication, Sir M Visvesvaraya Institute of Technology, Bangalore, India

Graduated – May 11

GPA-3.33

GPA-72.33/100